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CY28445-5
....................... Document #: 38-07739 Rev *C Page 3 of 25
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot
functionality
in
that
once
a
valid
low
on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
53
REF1/FCTSEL0
I/O, SE
PD
Fixed 14.318 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7
(DOT96[T/C], 27M-non-spread and Spread) and pin 10,11 (SRC[T/C]0 or
100M[T/C]_SST) (sampled on the VTT_PWRGD# assertion).
54
REF0/FSC
I/O
Fixed 14.318 MHz clock output / 3.3V-tolerant input for CPU frequency
selection.
Refer to DC Electrical Specification Table for VilFS_C, VimFS_C and VihFS_C
specifications
55
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
56
PCI_STP#
I, PU
3.3V LVTTL input for PCI_STP# active LOW.
57, 58, 63, 64 PCI[1:4]
O, SE 33 MHz clock outputs.
61, 67
VDD_PCI
PWR
3.3V power supply
62, 66
VSS_PCI
GND
Ground
65
PCI5/FCTSEL1
O, SE
PD
33 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7
(DOT96[T/C], 27M-non-spread and Spread) and pin10,11 (SRC[T/C]0 or
100M[T/C]_SST) (sampled on the VTT_PWRGD# assertion).
68
PCIF0/ITP_SEL
I/O, SE 33 MHz clock output / 3.3V LVTTL input to enable SRC[T/C]10 or
CPU[T/C]2_ITP on pin 36, 37. (sampled on the VTT_PWRGD# assertion).
0 = SRC10 (default)
1 = CPU2_ITP,
Pin Descriptions (continued)
Pin No.
Name
Type
Description
FCTSEL1 FCTSEL0 PIN 6
PIN 7
PIN 10
PIN 11
0
DOT96T
DOT96C
100MT_SST 100MC_SST
0
1
DOT96T
DOT96C
SRCT0
SRCC0
1
0
27M_non s pread 27M_Spread SRCT0
SRCC0
1
OFF Low
TBD
SRCT0
SRCC0
FCTSEL1 FCTSEL0 PIN 6
PIN 7
PIN 10
PIN 11
0
DOT96T
DOT96C
100MT_SST 100MC_SST
0
1
DOT96T
DOT96C
SRCT0
SRCC0
1
0
27M_non s pread 27M_Spread SRCT0
SRCC0
1
OFF Low
TBD
SRCT0
SRCC0
Table 1. Frequency Select Table FSA, FSB and FSC
FSC
FSB
FSA
CPU
SRC
PCIF/PCI
27MHz
REF0
DOT96
USB
1
0
1
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
133 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
166 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
0
200 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
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